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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2011-2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. wide optical spectrum laser power monitor ic isl58327 the isl58327 photo sensor ic has a wide optical spectral sensitivity from 400nm to 1000nm. it is good for multiple light source applications, such as laser based projectors. the isl58327 has two banks of three sets of gain registers. for a pico-projector application, the two banks of gain registers can be used to monitor the bias level and peak level of each wavelength. bank switching is done by applying a ttl compatible logic signal to the hl pin. the three sets of gain registers can be used to adjust optical-to-electrical conversion gain for each red, green, and blue laser or any waveleng th in a spectral range for application. the isl58327 is a si ngle die device that has a photo detector of 0.7mm diameter in the center of the die. the photo current signal is amplified through the tia, fine gain amplifier, and the output drivers to convert from current to voltage. the output of isl58327 can be configured to be either differential or single-ended. gain changing according to each wavelength is done through the i 2 c serial interface. registers can be updated in real time while the device is in operation. the isl58327 operates from a single +5v supply. it is available in a space-saving 9-ball glass top bga package. features ? high sensitivity from 400nm to 1000nm with patented technology for improved blue photo response ? differential voltage output or single-ended output ? internal output reference or external output reference ? serial interface for gain calibration ? fast settling time < 20ns ? wide signal bandwidth > 80mhz ? wide signal gain dynamic range > 20db ?low power consumption ? low output offset < 50mv ? small 9-ball optical chip scale package (ocsp) (3mmx3mm) ?i 2 c serial interface applications ? optical power monitoring ? laser based pico-proje ctors or projection tv ? laser auto power control for laser based application ? white balance for led based lc os and dlp pico projectors related literature ? see tb478 ?pcb assembly guidelines for shell-op 3d package? ito driver lcos driver laser diode driver power converter digital circuits dc/dc laser diode video front end and video processor 3.3v 2.5v 1.8v 1.2v 5.0v mcu oeic isl58327 optic feedback lcos panels figure 1. application block diagram july 29, 2013 fn6577.2 o bs o l e t e p r o d uct no re co m m e nde d r e p l ace m e nt c o n t a c t o u r t e c h n i c a l s u p p o r t ce n t e r a t 1 - 8 8 8 - i n t e rs i l o r w w w . i n t e r s i l . c o m / t s c
isl58327 2 fn6577.2 july 29, 2013 block diagram iv amp slow tail control outn vdd vref 0.1f gnd 0.1f +5.0v outp 10k scl a0 gnd gnd sda power & control slowtail_red 0 1 2 3 4 5 6 7 12 7 0x10-5 1 0 0 0x10-4 x 1 0 blu red grn select 12 12 slowtail_blu 0x1e 0 1 2 3 4 5 6 7 slowtail_ grn 0 1 2 3 4 5 6 7 7 7 tia_gain 0x1ch 0 1 2 3 4 5 6 7 tia gain control gain control slow tail reference control 0x10h 0 1 2 3 4 5 6 7 + - + - + - + - 0 1 blue gain hi (12bits) reg 0x12[7:0] +reg 0x11[7:4] 0 1 blue gain lo (12bits) reg 0x13[7:0] +reg 0x11[3:0] 0 1 red gain hi (12bits) reg 0x15[7:0] +reg 0x14[7:4] red gain lo (12bits) reg 0x16[7:0] +reg 0x14[3:0] green gain hi (12bits) reg 0x18[7:0] +reg 0x17[7:4] green gain lo (12bits) reg 0x19[7:0] +reg 0x17[3:0] 0 1 2 h/l hl chip_en tia_h tia_l select latch latch serial interface
isl58327 3 fn6577.2 july 29, 2013 pin configuration isl58327 (9 ball ocsp) top view 3 2 1 b a c vdd outn outp vss hl vref a0 scl sda pd pin descriptions pin number pin name type description a1 sda digital i/o i 2 c interface data, bi-directional b1 vref analog input reference voltage input c1 outp analog output positive swing analog output a2 scl digital input serial interface clock b2 hl digital input high/low gain mode selection, h = high gain, l = low gain. use in conjunction with reg 0x10 bit 7. * for hard switching, reg 0x10 bit 7 must be set to 1. * for soft switching, this pin must be high. c2 outn analog output negative swing analog output a3 a0 digital input i 2 c address a0; internally pulled down. b3 vss power gnd c3 vdd power +5.0v supply - pd optical input photo diode ordering information part number (notes 1, 2, 3, 4) package tape & reel (pb-free) pkg. dwg. # isl58327ciz-t7 9 ball ocsp s3x3.9 ISL58327CIZ-T7A 9 ball ocsp s3x3.9 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free wlcsp and bga packaged products employ special pb-free material sets; molding compounds/die attach mat erials and snagcu - e1 solder ball terminals, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free wlcsp and bga packaged products are msl classified at pb-free pe ak reflow temperatures that meet or exceed the pb-free requirem ents of ipc/jedec j std-020. 3. please refer to tb478 for solder profile. 4. for moisture sensitivity level (msl), please see device information page for isl58327 . for more information on msl please see tech brief tb363 .
isl58327 4 fn6577.2 july 29, 2013 absolute maximum rating s thermal information supply voltage (+5.0v to gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0v maximum cmos input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v maximum output voltage . . . . . . . . . . . . . . . . . . . . v ss - 0.3 to v dd + 0.3 esd rating human body model (per mil-std-883 method 3015.7). . . . . . . . . . . . . . . . . .2kv machine model (per eiaj ed-4701 method c-111) . . . . . . . . . . . . . 200v latch up (tested per jesd-78; class ii; level a). . . . . . . . . . . . . . . . 100ma thermal resistance (typical, note 5) ? ja (c/w) 9 ld ocsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-25c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 5. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. electrical specifications v dd = 5.0v, t a = +25c unless otherwise specified. parameter description conditions min (note 6) typ max (note 6) unit v dd supply voltage 4.5 5.0 5.5 v t a ambient temperature 0 25 85 c t die die temperature 0 50 125 c dc electrical specifications v dd = 5.0v, t a = +25c unless otherwise specified. parameter description conditions min (note 6) typ max (note 6) unit i vdd1 supply current no incident light, in normal mode 20 25 ma i vdd1 supply current no incident light, in sleep mode 600 a v ofs output offset, referenced to vref no incident light -50 9 +50 mv v ref_i common mode output voltage internal vref generator 1.75 2.35 v v il cmos input low sda, scl, and hl pins v gnd 0.8 v v ih cmos input high sda, scl and hl pins 3.3 5.0 v ac electrical specifications v dd = 5.0v, t a = +25c unless otherwise specified. parameter description conditions min (note 6) typ max (note 6) unit v outmax differential mode output voltage (outp) ? (outn) linear output 2.95 v p-p bandwidth bandwidth outp, outn (not differential) -3db rbw = 30khz 85 mhz
isl58327 5 fn6577.2 july 29, 2013 sensitivity v dd = 5.0v, t a = +25c unless otherwise specified. parameter description conditions min (note 6) typ max (note 6) unit gain 00 tia lowest gain (445nm) 0db fine gain adjustment, 7ffh differential output 350 450 550 mv/a gain 01 tia 2nd lowest gain (445nm) 0db fine gain adjustment, 7ffh differential output 700 890 1100 mv/a gain 10 tia 2nd highest gain (445nm) 0db fine gain adjustment, 7ffh differential output 1400 1790 2170 mv/a gain 11 tia highest gain (445nm) 0db fine gain adjustment, 7ffh differential output 3700 4850 6020 mv/a gain fine_max maximum fine gain for both high gain and low gain channels compared to 0db fine gain setting, 7ffh 19 db gain fine_min minimum fine gain for both high gain and low gain channels compared to 0db fine gain setting, 7ffh -5.5 db current to optical conversion: optical sensitivity is not tested in production. gain parameters were obtained using input test currents. the following factors are used to convert current to optical power. i2o 450nm current to optical conversion (450 nm) bench data; measured on typical devices 0.27 a/w i2o 530nm current to optical conversion (530 nm) bench data; measured on typical devices 0.26 a/w i2o 640nm current to optical conversion (640 nm) bench data; measured on typical devices 0.38 a/w serial interface ac performance v dd = 5.0v, t a = +25c unless otherwise specified. parameter description conditions min (note 6) typ max (note 6) unit c i input capacitance 10 pf f scl scl clock frequency 400 khz input leakge input leakage scl and sda pin -20 20 a note: 6. parameters with min and/or ma x limits are 100% tested at +25c, unless otherw ise specified. temperature limits established by characterization and are not production tested.
isl58327 6 fn6577.2 july 29, 2013 i/o pins equivalent circuits pins type equivalent circuit sda scl digital i/o digital input a0 digital input h/l digital input vref analog input outp outn analog output vdd pad vss vdd pad vss 1m vdd pad vss 500 vdd pad vss 20k vdd pad vss 50
isl58327 7 fn6577.2 july 29, 2013 vdd power i/o pins equivalent circuits (continued) pins type equivalent circuit vdd vss esd clamp
isl58327 8 fn6577.2 july 29, 2013 application information input optical power the isl58327 has a photo detector in an octagon shape (shown in pd pattern) with 700m diameter. it is sensitive from 400nm to 1000nm for light power monitoring application, which is a perfect choice for light automatic power control. this wide range of sensitivity also allows the isl58327 to be used for white balance control in systems such as led based lcos or dlp pico projectors. current generated by the photo detector, is amplified by a trans-impedance amplifier (tia). the tia has four feedback resistors; the user can choose whic h feedback resistor is used for high or low gain applications by the setting in tia_gain register. once an appropriate resistor is se lected for the required tia gain, the optical signal is then amplified by the tia, which feeds into the fine gain stage. high gain channel and low gain channel tia gains can be individually set through the tia register. the high gain and low gain channels have the same gain adjustment range (20db) and can be individually controlled. in applications, if light power is modulated between 2 power levels, the user can choose between high gain channel for low power level and low gain channel for high power. it can provide the best resolution when power is low yet the amplifier circuit is not saturated when the power is high. if users do not need to monitor two power levels, there is no need to switch between the high gain channel and low gain channel. the selection of high gain or low gain signal path can be done with fast hardware switching or by setting the register bit ?h/l?. when changing high gain or low gain signal paths by hardware switching, ?h/l? bit needs to be ?1?; when changing it with the register (soft switching), the hl pin needs to be driven by digital high because hl and ?h/l? are and?ed for tia gain control. regardless of the channel gain settings, the dynamic range of tia is determined by the photo detector sensitivity with respect to wavelength. for example, in a 445nm application when tia = 01b gain is selected, the maximum input optical power is limited to 2mw for blue light laser, but this limita tion is reduced to 1.45mw with a 638nm laser. this is because the photo detector has a higher optical-to-electrical conversion efficiency at longer wavelengths. higher than the maximum input limitation, the tia or whole device will still be working but it may yield a distorted output and a long falling time, while the circuits recover from saturation. detector pattern gain control the isl58327 channel gain is set through a 12-bit dac, separated into 2 registers. each wavelength has two 12-bit gain registers; one for high gain applications and the other for low gain applications. the selection of high gain or low gain is done by fast hardware switching through the hl pin or ?h/l? register bit. all gain registers of high gain and low gain channels are capable of update at anytime through the serial interface. the 12-bit gain registers provide a total of 25db of adjustment range; +16db to -5.5db reference to fine gain setting 7ffh. all settings will be reset to default at power-on. the user needs to load all gain settings after the isl58327 is powered up. overall differential output signal gain can be estimated by using equations 1 through 3: blue laser diode(445nm) red laser diode (638nm) green laser diode(530nm) where: code is 12 bits fine gain code in decimal (0 ~ 4095) and tia is the factor shown in table 2. output configuration the isl58327 has two differential outputs: outp is a positive and outn is a negative swing output. outp and outn outputs are referenced to vref. vref can be externally supplied or from the internally generated 2.1v. with respect to the input optical signal, outp swings up from the reference voltage and outn swings down from the reference voltage. both outp and outn have the same linear output dynamic range up to 1.4v swing table 1. maximum input power vs tia resistor tia_gain (tia_h/tia_l) (445nm) mw (638nm) mw (532nm) mw 00b 5.0 3.65 5.30 01b 2.5 1.82 2.65 10b 1.25 0.91 1.33 11b 0.44 0.32 0.47 table 2. tia factor in equations tia_h, tia_l settings tia factor in equation 00b 500 01b 1000 10b 2000 11b 5400 300m 300m 700m 700m ? w ? 1.88 tia ? 256 code + ------------------------------ - = (eq. 1) gain (mv/ ? w ? 2.57 tia ? 256 code + ------------------------------ - = (eq. 2) gain (mv/ ? w ? 1.76 tia ? 256 code + ------------------------------ - = (eq. 3)
isl58327 9 fn6577.2 july 29, 2013 from the reference voltage. when using an external reference voltage, the user needs to adjust the gain registers to set proper channel gain to prevent output saturation. to use isl58327 as a single-ended output, the user can take either outp or outn signal and load the unused output with the equivalent resistor and capacitor load to keep both outputs with the same loading condition. however, it is acceptable to leave the unused output floating. it is not recommende d to use vref as a reference source to drive other devices. to obtain the best signal quality at the input of the afe, it is reco mmended to keep outp and outn traces in parallel and to keep them with same length, width, and routing. if output signals from isl58327 need to travel through a flex cable to the afe, matching with the impedance of flex cable is necessary. the best value should be determined according to the actual application. slow tail compensation photons at longer wavelengths wi ll penetrate deeper into the photo detector structure than photons at shorter wavelengths. it takes more time for electron-hole pairs to become photo current and results in longer response of pulse outputs, called slow tail. longer wavelength light such as 638nm or ir has more visible slow tail effect than blue light. to minimize the slow tail effect, isl58327 has incorporated intersil?s proprietary slow tail compensation technology. there are three registers for slow tail compensation adjustment for ea ch wavelength (638nm, 532nm, and 445nm). slow tail compensation function is not limited to the specific wavelength listed prev iously; it is in conjunction with the selected fine gain registers. the user can disable slow tail compensation by setting bit 7 (msb ) of the register to ?0?. this function can also be used to improve the quality of the pulse output waveforms due to impedance mismatch from the oeic outputs to the flex. one example is to improve tr/tf or to minimize overshoot. layout consideration when using differential output, layout the outp and outn traces next to each other. the ground trace should be placed to another side of the outp and outn traces. when using single-ended, the reference trace needs to be laid out next to the output signal trace. the ground trace should be laid out on the other side of the output. for best results, a dual la yer flex with signal on one side and the ground plane on another side is a must. reference voltage the isl58327 has a built-in reference voltage generator to generate 2.1v reference voltage for all circuit blocks. output is biased at the internal referenc e voltage automatically when the vref pin is left floating. when a dc voltage is applied to the vref pin, outp and outn will be biased at the external reference voltage. external reference should be within the range of 1.5v to 2.5v. outside of this range may yield distorted outputs. when using external reference voltage, good decoupling is very important to prevent noise coupling into vref. a 0.1f ceramic capacitor placed as close to the vref pin as possible is recommended to decouple vref to ground. power supply decoupling due to the current being switched rapidly at outp and outn, it is important to ensure that the power supply is well decoupled to ground. during output switching, the v dd undergoes severe current transients, thus every effo rt should be made to decouple the v dd as close to the package as possible. without proper power supply decoup ling, the result could be poor rise/fall times, overshoot, and poor settling response. sensitivity curves figure 2. normalized spectr al response vs wavelength figure 3. intensity vs output (red led 620nm; green led 532nm; blue led 460nm) 0 0.2 0.4 0.6 0.8 1.0 1.2 300 400 500 600 700 800 900 1000 wavelength (nm) normalized spectral response
isl58327 10 fn6577.2 july 29, 2013 register map addr name b7 b6 b5 b4 b3 b2 b1 b0 default access 00h id0 device id 27h r 01h id1 device option device version e0h r 02h reserved 03h reserved for multi-chip protocol 04h reserved for multi-chip protocol 05h reserved for multi-chip protocol 06h reserved for multi-chip protocol 07h reserved for multi-chip protocol 08h reserved for multi-chip protocol 09h reserved for multi-chip protocol 0ah reserved for multi-chip protocol 0bh reserved for multi-chip protocol 0ch reserved for multi-chip protocol 0dh reserved for multi-chip protocol 0eh reserved for multi-chip protocol 0fh reserved for multi-chip protocol 10h control h/l deglitch_b blue red/green test_en x x chip_en 06h rw 11h b _gain0 blue_h[3: 0] blue_l[3:0] ffh rw 12h b_h_gain blue_h[11:4] 7fh rw 13h b_l_gain blue_l[11:4] 7fh rw 14h r_gain0 red_h[3:0] red_l[3:0] ffh rw 15h r_h_gain red_h[11:4] 7fh rw 16h r_l_gain red_l[11:4] 7fh rw 17h green_gain0 green_h[3:0] green_l[3:0] ffh rw 18h green_h_gain green_h[11:4] 7fh rw 19h green_l_gain green_l[11:4] 7fh rw 1ah st_red st_en_red st_time_red[2:0] x st_mag_red[2:0] 00h rw 1bh st_green st_en_green st_time_green[2:0] x st_mag_green[2:0] 00h rw 1ch tia_gain x x x x tia_h[1:0] tia_l[1:0] 00h rw 1dh reserved 1eh st_blue st_en_blue st_time_bl ue[2:0] x st_mag_blue[2:0] 00h rw note: all gain registers in this table can be used for any wave length in spectral range from 390nm to 1000nm, not limited to wa velengths specified.
isl58327 11 fn6577.2 july 29, 2013 register description table 3. id0 (addr = 00h) register description id0 device id, read only, code = 27h table 4. id1 (addr = 01h) register description device option device option code, read only, code = e0h device version device version code, read only, code = 0h table 5. control (addr = 10h) register description h/l high gain or low gain channels selection. used in conjunction with hl pin. 1b: high gain channel 0b: low gain channel default: 0b deglitch_b 1b: disable serial interface deglitch function 0b: enable serial interface deglitch function default: 0b blue 1b: device works in blue mode (regardless of red/green bit setting) 0b: device works in either red or green mode, depends on red/green register bit setting default: 0b red/green 0b: green 1b: red default: 0b (green mode) test_en to enable a chip test function (for intersil internal use only) 1b: enable test function 0b: disable test function default: 0b chip_en to enable or disable isl58327. when disabled all outputs are in hi-z 1b: enable 0b: disable (sleep mode) table 6. b_gain0 (addr = 11h) register description blue_h[3: 0] lower 4 bits of blue light high gain channel fine gain control blue_l[3: 0] lower 4 bits of blue light low gain channel fine gain control table 7. b_h_gain (addr = 12h) register description blue_h[11:4] high 8 bits of blue li ght high gain channel fine gain control table 8. b_l_gain (addr = 13h) register description blue_l[11:4] high 8 bits of blue light low gain channel fine gain control table 9. red_gain0 (addr = 14h) register description red_h[3: 0] lower 4 bits of red light high gain channel fine gain control red_l[3: 0] lower 4 bits of red light low gain channel fine gain control table 10. red_h_gain (addr = 15h) register description red_h[11:4] high 8 bits of red light high gain channel fine gain control table 11. red_l_gain (addr = 16h) register description red_l[11:4] high 8 bits of red light low gain channel fine gain control table 12. green_gain0 (addr = 17h) register description green_h[3:0] lower 4 bits of green li ght high gain channel fine gain control green_l[3:0] lower 4 bits of green light low gain channel fine gain control table 13. green_h_gain (addr = 18h) register description green_h[11:4] high 8 bits of green lig ht high gain channel fine gain control table 14. green_l_gain (addr = 19h) register description green_l[11:4] high 8 bits of green light low gain channel fine gain control table 15. st_red (addr = 1ah) register description st_en_red red light slow tail compensation control 1b: enable 0b: disable (when disable, st_time_red and st_mag_red are reset to 000b) st_time_red red light slow tail co mpensation time constant control st_mag_red red light slow tail compensation magnitude control
isl58327 12 fn6577.2 july 29, 2013 table 16. st_green (addr = 1bh) register description st_en_green green light slow tail compensation control 1b: enable 0b: disable (when disabled, st_time_green and st_mag_green are reset to 000b) st_time_green green light slow tail compensation time constant control st_mag_green green light slow tail compensation magnitude control table 17. tia_gain (addr = 1ch) register description tia_l[1:0] tia gain selection in low gain channel application 00b: lowest gain 01b: 2nd lowest gain 10b: 2nd highest gain 11b: highest gain tia_h[1:0] tia gain selection in high gain channel application 00b: lowest gain 01b: 2nd lowest gain 10b: 2nd highest gain 11b: highest gain table 18. st_blue (addr = 1eh) register description st_en_blue blue light slow tail compensation control 1b: enable 0b: disable (when disable, st_time_blue and st_mag_blue are reset to 000b) st_time_blue[2:0] blue light slow tail compensation time constant control st_mag_blue[2:0] blue light slow tail compensation magnitude control
isl58327 13 fn6577.2 july 29, 2013 serial interface protocol i 2 c interface the device address of the i 2 c bus of the isl58327 is a 7 bits fixed address 0011_10(a0)xb, where (a0) can be hard wired. note that (a0) is internally pulled down. when 001110(a0)x with x as r or w is sent after the start condition, this device compares the first seven bits of this byte to its address and matches. since scl and sda lines of the i 2 c bus are either open collector or open drain, 2 pull-up resistors (rp)on bus for scl and sda are necessary. to minimize crosstalk and to minimize spikes, a serial termination resist er (rs) close to the scl and sda lines are important for each device on the i 2 c bus. the value of rp and rs is determined according to the maximum sink current of the device, supply voltage, bus capacitance, and the number of devices on the bus. even though the maximum bus capacitance of the fast mode specified in the i 2 c bus is 400pf, it is always recommended to reduce bus capacitance to get better signal quality. figure 4 shows a sample one-byte read. figure 5 shows a sample one-byte write. for more information about the i 2 c standard, please consult the philips? i 2 c specification documents. figure 4. i 2 c read timing diagram sample start w a a a6 a5 a4 a3 a2 a1 a0 w a r7 r6 r5 r4 r3 r2 r1 r0 a a6 a5 a4 a3 a2 a1 a0 w a a a a d7 d6d5d4 d3d2 d1d0 1357 1357 123 45 6 9 2 4 6 stop start sda driven by master device address sda driven by isl58327 data byte0 register address out device address i 2 c data sda driven by master sda driven by master 2468 924689 78135789 i 2 c sda i 2 c sda i 2 c clk in figure 5. i 2 c write timing diagram sample start w a a a6 a5 a4 a3 a2 a1 a0 w a r7r6r5r4r3r2r1r0 a b7b6b5b4b3b2b1b0 a a 12615948 stop sda driven by master functions register address device address sda driven by master sda driven by master i 2 c data i 2 c sda in i 2 c sda out i 2 c clk in aa 345 7 89 234 678 12 3 5 67 9 a
isl58327 14 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6577.2 july 29, 2013 for additional products, see www.intersil.com/product_tree about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change july 29, 2013 fn6577.2 changed product information verbiage to about intersil verbiage. february 21, 2012 fn6577.1 added ISL58327CIZ-T7A to ?ordering information? on page 3. august 30, 2011 fn6577.0 initial release.
isl58327 15 fn6577.2 july 29, 2013 package outline drawing s3x3.9 3x3 array 9 bump optical chip scale package (ocsp) rev 7, 10/10 notes: bottom view side view typical recommended land pattern top view seating plane 31 2 b c a b a a1 a1 c 0.10 c 0.10 c c cab m m 0.15 0.08 5 2.155 0.025 2.155 0.025 1.30 0.65 1.30 0.65 0.825 0.045 1.045 max 0.30 0.03 (1.30) (0.65) (1.30) (0.65) (0.30) 0.16 0.03 dimensions are in millimeters. dimensioning and tolerancing conform to asme y 14.5m-1994 primary datum c and seating plan e are defined by the spherical 1. 3. 2. 4. pin "a1" is marked on the top and bottom side adjacent to the 5. crowns of the contact balls. dimensions in ( ) for reference only. dimension is measured at the maximum ball diameter. a1 ball. corner corner

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